2-phase switched capacitor DC-DC charge pumps are frequently used to generate voltages other than the supply voltage in integrated circuits because of the simple control circuit. This kind of circuit has been widely applied in programming flash memories, driving liquid crystal displays (LCDs), etc., where a high electric field is required. Among various conventional switched capacitor charge pumps, a cross-coupled charge pump structure has been very popular because of its high efficiency. Moreover, such charge pumps can be implemented with a conventional complementary metal-oxide-semiconductor (CMOS) process because the voltage difference between gate, source and drain of the metal-oxide-semiconductor field-effect transistor (MOSFET) does not exceed the supply voltage VDD. If desired, a high output voltage can be achieved by cascading the single stage to have multiple cascading stages.
There have been attempts to improve the performance of the cross-coupled charge pump. One conventional implementation adds a voltage doubler circuit to each stage of the cross-coupled charge pump to maintain the overdrive voltages of the charge transfer switches (CTSs) at different loading currents. Such implementation can achieve better driving capability because the overdrive voltages of the N-type metal-oxide-semiconductor (NMOS) CTSs do not degrade at high loading current condition. However, this implementation is also limited to the NMOS transistor CTS of the cross-coupled charge pump, while the P-type metal-oxide-semiconductor (PMOS) transistor CTS(s) of the cross coupled charge pump still suffer from decreased overdrive voltage problem under high loading current condition.
Another conventional implementation makes use of four auxiliary gate voltage boosting circuits in each stage of the cross coupled charge pump to achieve high overdrive voltages for all the CTSs. However, this implementation of the boosting circuits requires large silicon area. Furthermore, the clock signals that drive the boosting circuits are required to have amplitudes equal to 2VDD, which are required to be generated by a separate voltage doubler circuit. As a result, this conventional implementation is not only silicon inefficient, the additional boosting circuits and voltage doubler circuit for clock signal generation will consume power and decrease the overall efficiency of the charge pump circuit.
Still another conventional implementation for cross coupled charge pumps makes use of four and six phase clock signals to drive the cross coupled charge pump circuits in an effort to achieve improved efficiency under different loading current condition. However, these conventional implementations involve more complicated clock signals, which result in higher the switching losses, higher power consumption, and requires a larger silicon area to implement the control circuit. As a result, a multiple phase control circuit is not in favor for compact and power efficient cross coupled charge pump circuits.
The above-described deficiencies of today's charge pumps are merely intended to provide an overview of some of the problems of conventional systems, devices and methods, and are not intended to be exhaustive. Other problems with the state of the art and corresponding benefits of some of the various non-limiting embodiments may become further apparent upon review of the following detailed description.